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LPC55S69 : CASPER and Core1

Question asked by Eugene Hiihtaja on Oct 29, 2019
Latest reply on Oct 30, 2019 by ZhangJennie

Hello !


In UM mentioned:


ARMv8-M architecture (ARM M33) introduces co-processor interface allowing CASPER
access via MCR (Move from Coprocessor to Register) and MRC (Move from Register to
Coprocessor) opcodes. Using this, up to two registers can be transferred between ARM
M33 core and CASPER.



If Casper act as coprocessor and Core1 dosn't supports coprocessors, it means CASPER can't be used from Core1 ?

Is this so ?


MPU, FPU, DSP, ETM, Trustzone (SECEXT), Secure Attribution Unit (SAU) or co-processor interface are not avaible on Core1.


What other peripherals can't be used from Core1 ?


What areas of SRAM are recommended for code execution for Core1 ?