AnsweredAssumed Answered

LPC4370 ADCHS high interrupt jitter

Question asked by Vitaliy Livnov on Oct 27, 2019
Latest reply on Nov 13, 2019 by Vitaliy Livnov

Hello.

Our application uses HSADC and DMA to write samples to RAM. We also use threshold crossing interrupt to search signal edges.

We achieved the minimum HSADC ISR calling delay by moving the interrupt table and handler to RAM. Now it is about 100 ns. However, this value can only be obtained if the microcontroller is in interrupt wait mode (__WFI()) before it is triggered. If the microcontroller performs any functions before the interrupt is triggered, the delay time becomes unstable and can take values from 100 ns to 2 μs.

Using code optimization and transferring all software to RAM improves stability a little, but does not completely solve the problem. Tell us, please, how to get around this problem?

Outcomes