Does any small SRAM area exists what can keep context over softreset/worm reboot ?
No matter what the Reset is for example hardware reset, software reset, POR reset..., the PC value will be fetched from a fixed place, stack point is initialized to a fixed position, in other words, the Reset operation does not need to preserve context, so the RAM is unnecessary. But for some chips, the Reset source can be saved into a register.
Hope it can help you
Yes it is no need for normal MCU usage. But for example K82 MCU have VBAT register file what retain context over reboot. It is very useful feature if you need to reboot MCU and would like to save some states in SRAM.
Is LPC55x have this kind of SRAM area ?
Regarding your question, the LPC55S6x has the similar registers in RTC module, which is powered by the VBAT pin. If the main power is down, but the VBAT pin is powered, the data in the registers retain.
The registers are called "RTC general purpose registers 0 to 7 (GPREG[0:7], offset 0x40:0x5C)"
Hi XiangJun Rong !
Oh, yes this feature is very important for us.
What do you think if we can save someting ( 256 bytes or even less) if BoD interrupt is detected.
E.g if total real power loss is happens, to what level Flash memory is stay unlocked and we have change to write minimal amount of information ?
Or LPC have some other nonvolatile storage what can be updated in last moment ?
Looks like minimal erasable flash unit is 32KB but we can write to preerased space for sure.
Is this doable ?
I think it is okay to erase/program flash after the BOD interrupt is detected. The internal flash has internal boost circuit to increase the flash power voltage, so it is okay to erase/program flash in low VDD power voltage. I think you can connect a large by-pass capacitor on VDD so that the VDD can keep longer time when power off.
But can I write something from Core1 to flash memory when Core0 on PowerDown mode ?
Or I should wakeup it and execute Flash write via it ?
BoD processed on Core1 and I should remember this some how.
wakeup of Core0 take 350us at list plus some SW routines.
may be it is not so much time remains.
It is okay for the CORE1 of LPC55S6x to write flash by calling the IAP function, but the problem is that the lpc has enough time to erase/program flash before power down.
Retrieving data ...