I need to use the FMC (FLASH Memory Controller) module to write the flash and the eeprom.
The first thing required is the FCLKDIV clock divider which must be set correctly based on table 18-2.
The choice depends on the BUSCLK clock.
1) What is the default BUSCLK value?
Going deeper we see that if we are in the FEI mode (FLL engaged internal) that is the default mode and the internal reference clock should be set to 32KHz thanks also to the factory settings of the SCTRIM and SCFTRIM registers, which I do not need to change.
At this point the clock enters the FLL but it is not clear what the output value should be, it says that is in the range 32MHz-40MHz (ICSFLLCLK).
BUSDIV = 0; and BDIV = 0x1 (so the clock is divided by two).
So the output bus clock should be between 16MHz and 20 MHz.
2) What is the correct value? Between 16MHz and 20 MHz the value of FCLKDIV changes.
3) What could be the problem with an incorrect FCLKDIV? is the data retention guaranteed anyway?