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SJA1105P REF_CLK configuration

Question asked by Mark Schickedantz on Oct 17, 2019
Latest reply on Oct 21, 2019 by Bulat Karymov

I am working on a custom board with a SJA1105P with three ports connecting to PHYs (MAC mode) and two ports connecting to MACs (PHY mode).  All ports are connected as RMII interfaces.  I'm clocking the switch with a 25MHz oscillator and want to clock the PHYs and MACs with 50MHz clocks from the switch REF_CLK outputs.

 

The product data sheet (SJA1105PQRS) states in section 6.2.2 RMII Signaling - "In both the PHY-MAC (i.e. PHY to switch) and MAC-MAC (i.e. processor to switch) configurations, the REF_CLK output on the Ethernet switch can provide the shared reference clock."

 

The application hints document (AH1704) states in section 5.1.1 Selectable Clock Sources - "IO pad (TXC, REF_CLK, TX_CLK) refered to as TX_CLK_x(02h*x)  This can operate as either and output (RGMII, RMII-MAC, MII PHY) or as input (RMII-PHY, MII-MAC)."  I take this to mean that the REF_CLK pin is an output in RMII MAC mode and an input in RMII PHY mode which contradicts the information in the data sheet.

 

Can the REF_CLK pins, in fact, provide 50MHz clocks when connected to external MACs (processors) in RMII PHY mode and how do I configure it?

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