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What is the max frequency for MCGFFCLK?

Question asked by Matt Boytim on Oct 16, 2019
Latest reply on Oct 18, 2019 by Matt Boytim

If you aren't using the FLL can the MCGFFCLK be configured to be higher than 39.0625 kHz?  I am using an old mcg driver where pll_init() sets the MCGFFCLK to less than 39.0625 kHz even though I am using the PLL not the FLL.  The logic is like this:

 

// the max frequency for the FLL reference is 39.0625kHz so the MCG FF clock should not exceed that
if      (crystal_val <= 1250000) {frdiv_val = 0;} // fmax = 1250000/32 = 39062.5
else if (crystal_val <= 2500000) {frdiv_val = 1;} // fmax = 2500000/64 = 39062.5
else if (crystal_val <= 5000000) ...

 

I didn't chase down the details in the latest KSDK but I did see this comment

 

* When porting to a new board, set the following members
* according to the board setting:
* 1. frdiv: If the FLL uses the external reference clock, set this
* value to ensure that the external reference clock divided by frdiv is
* in the 31.25 kHz to 39.0625 kHz range.

 

Here it says *if the FLL uses the external reference* - but I am not using the FLL.

 

My MCGFFCLK is 23437.5 Hz but I would like to double it so there is an integer number of cycles per second but then it would exceed 39.0625 kHz.

 

Thanks,

 

Matt

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