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JTAG SEQUENCE - CW TAP

Question asked by Prashant Soni on Oct 15, 2019
Latest reply on Oct 25, 2019 by Yiping Wang

Hi NXP Team 

 

We have coustom build LS2088A board, in which CPLD is bypassed, but at the time we want to  DDR SPD read from CW tap we are facing issue.

Can you please let us know the reset sequence to be followed at this DDR SPD read from CW TAP  operation.

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