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CKE control of RT1052 SEMC

Question asked by tom fang on Oct 14, 2019
Latest reply on Oct 31, 2019 by tom fang

Hi Guys,

Do you know how to control the CKE and CLK signals from SEMC module? I'm connecting a SDRAM (AS4C8M16S, clock = 72MHz) with it, everything works perfect except for the power up timing of CKE and CLK. As the SDRAM chip requirement, CKE should be pulled high after maintaining a 200us stable CLK, but both signals start up at the same time and somehow CLK is  suppressed for a while. I checked RT1050 reference manual and didn't find any register about it (only CKEOFF is mentioned in SDRAMCR1, but I don't think it works for this case).

SDRAM_CKE and SDRAM_CLK

 

SEMC settings:

uint32_t ClockCycleNs = 13;
static const uint32_t RefreshCycleNs = (64*1000*1000) / 4096;
sdramconfig.memsize_kbytes = 16MBytes / 1024;
sdramconfig.portSize = kSEMC_PortSize16Bit;
sdramconfig.burstLen = kSEMC_Sdram_BurstLen8;
sdramconfig.columnAddrBitNum = GetColBitsFromNum( 9 );
sdramconfig.casLatency = GetCasLatencyFromNum( 3 );
sdramconfig.tPrescalePeriod_Ns = 1 * (16 * ClockCycleNs);
sdramconfig.tPrecharge2Act_Ns = 30;
sdramconfig.tAct2ReadWrite_Ns = 30;
sdramconfig.tRefreshRecovery_Ns = 70;
sdramconfig.tWriteRecovery_Ns = 4 * ClockCycleNs;
sdramconfig.tCkeOff_Ns = 45;
sdramconfig.tAct2Prechage_Ns = 45;
sdramconfig.tSelfRefRecovery_Ns = 75;
sdramconfig.tRefresh2Refresh_Ns = 50;
sdramconfig.tAct2Act_Ns = 16;
sdramconfig.tIdleTimeout_Ns = 0;
uint32_t TargetNs = RefreshCycleNs / 2;
uint32_t Factor = TargetNs / sdramconfig.tPrescalePeriod_Ns;
Factor = Factor ? Factor : 1;
sdramconfig.refreshPeriod_nsPerRow = Factor * sdramconfig.tPrescalePeriod_Ns;
sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;
sdramconfig.refreshBurstLen = 1;

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