ADC Calibration Related Issue for mpc5777c

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ADC Calibration Related Issue for mpc5777c

1,328 Views
vignesh_v
Contributor III

Hi,

    Im using eqadc  module for ADC . Without Calibration it was working fine. But there are some deviations from ADC values and hence decided to use the calibration as suggested in AN2989 . followed the example given below

Example MPC5676R-eQADC_PMC_chnl_conv+calib CW210  

but the issue is it gets 

stuck either in while (EQADC_A.FISR[0].B.EOQFX !=1) {} /* Wait for End Of Queue flag */

or

while (EQADC_A.FISR[0].B.RFDFX != 1){}

line in convert channel

There was an issue with qsort function as library support error was there and i also included own sort function but still same result.

If I comment those two lines seems to work but its wrong so i kindly request to know possible reason for the same.

int32_t EQADC_PowerUpCalibration(void)
{
unsigned long raw_res75, raw_res25;
unsigned long cal_res75, cal_res25;

float gccf, occf;

unsigned short gain;
short offset;

/* Convert channel 43 (75%VRH)with CAL=0 */
raw_res75 = ConvertChannel_Median(43,0);
/* Convert channel 44 (25%VRH)with CAL=0, 64 sample time (errata) */
raw_res25 = ConvertChannel_Median(44,0);

/* Compute Gain and Offset */
gccf = (float)(8192.0)/(raw_res75 - raw_res25);
gain = gccf * 16384;
occf = (float)(IDEAL_RES75 - (gccf * raw_res75) - 2.0);
offset = occf;

/* now store Gain in ADCn_GCCR */
EQADC_A.CFPR[0].R = (gain<<8) | 0x00000004;
/* now store offset in ADCn_OCCR */
EQADC_A.CFPR[0].R = ((unsigned short)offset << 8) | 0x00000005;

/* now store Gain in ADCn_AGR */
EQADC_A.CFPR[0].R = (gain<<8) | 0x00000031;
/* now store offset in ADCn_ACR */
EQADC_A.CFPR[0].R = ((unsigned short)offset << 8) | 0x00000032 | 0x80000000;

EQADC_A.CFCR0.R = 0x0410; /* Trigger CFIFO 0 using Single Scan SW mode */
while (EQADC_A.FISR[0].B.EOQFX !=1) {} /* Wait for End Of Queue flag */
EQADC_A.FISR[0].R = 0x10000000;

cal_res75 = ConvertChannel(43,1);
cal_res25 = ConvertChannel(44,1);

// Check the results
if ((ABS(cal_res75 - IDEAL_RES75) > 0xF) || (ABS(cal_res25 - IDEAL_RES25) > 0xF))
{
/* error */
return 1;
}

return 0; /* no error */
}

uint32_t ConvertChannel(int32_t channel, int32_t bCal)
{
uint32_t ret = 0;

/* Conversion command: convert "channel" */
/* with ADC0, set EOQ, and send result to RFIFO 0 */
/* 128 adc clocks sampling */
EQADC_A.CFPR[0].R = 0x800C0000 | (channel<<8) | (bCal<<24);
EQADC_A.CFCR0.R = 0x0410; /* Trigger CFIFO 0 using Single Scan SW mode */
/* Wait for RFIFO 0's Drain Flag to set */
while (EQADC_A.FISR[0].B.RFDFX != 1){}

ret = EQADC_A.RFPR[0].R;

/* Clear RFIFO 0's Drain Flag */
/* Clear CFIFO's End of Queue flag */
/* RFDF + EOQF */
EQADC_A.FISR[0].R = 0x10020000;

return ret;
}

uint32_t ConvertChannel_Median(int32_t channel, int32_t bCal)
{
uint32_t results[21];

int32_t i = 0;
for(i=0;i<sizeof(results)/sizeof(results[0]);i++)
{
results[i] = ConvertChannel(channel, bCal);
}

/* sort results */
qsort((void*)results,11,sizeof(results[i]),Compare);

return results[10]; /* median */
}

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1,028 Views
vignesh_v
Contributor III

Hi,

   I have attached code can u pl look into it and say ur suggestions mainly for EQADC A because for EQADC B its working.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

I have just reworked the example to eQADC_A. It works very well, I haven't found any difference in comparison to eQADC_B.

https://community.nxp.com/docs/DOC-344713 

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vignesh_v
Contributor III

Hi David,

               Thanks for the example but still it is stuck in the same line. I made some modifications after which I was able to get that stuck issue solved. But I  have issues with calibrated data for A and B ADC modules.

1. For EQADC_A the values are not calibrated.

2. For EQADC_B the values are calibrated but when range goes below 0.1 I'm not getting proper values. also sometime when voltages are above 2.5 some times randomly there are variations.

Request ur help on this.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

I just updated the example, there was another small error, I forgot to set CAL bit in the example conversion.

pastedImage_4.png

Then it works fine with eQADC_B. eQADC_A is not calibrated with the example code, you will have to apply the same code also for eQADC_A to get it calibrated.

Are you using EVB or your own prototype board?

Also I would note that ANB8-23 & ANB40-44 inputs are clamped to VDDEH7. If you want 0-5V range on ADC inputs ANB8-23 & ANB40-44, you must power VDDEH7 with 5V.

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davidtosenovjan
NXP TechSupport
NXP TechSupport
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davidtosenovjan
NXP TechSupport
NXP TechSupport

Also there is a minor issue with qsort calling:

pastedImage_1.png

Otherwise it seems to work fine.

I will share complete example early.

Thanks for your inputs, hope it helps

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi, I have tried to port it myself founded CFCR0 register is redefined for some reason, now containing two command FIFOs

pastedImage_3.png

So the line:

EQADC_A.CFCR0.R = 0x0410; /* Trigger CFIFO 0 using Single Scan SW mode */

must be now

EQADC_A.CFCR0.R = 0x04100000; /* Trigger CFIFO 0 using Single Scan SW mode */

to fit CFIFO0

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