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ONOFFpin debounce time

Question asked by on Oct 7, 2019
Latest reply on Oct 8, 2019 by gusarambula



The i.MX 7 Dual Applications Processor Reference Manual Dumb PMIC mode is described as follows.


Debounce—the debounce configuration supports 0 ms, 50 ms, 100 ms, and 500 ms.
The debounce is used to generate the set_pwr_off_irq interrupt. While it is in the ON state and the button is pressed longer than the debounce time, the set_pwr_off_irq is generated.


On the other hand, Figure 6-7. About FSM
The condition for transition from the OFF state is described as button pressed (any duration).
Can the debounce time be set in the same register for the transition from the ON state and the transition from the OFF state?


best regards