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imx6 solo power up sequence, leakage from peripheral

Question asked by Diego Perez on Oct 7, 2019
Latest reply on Oct 7, 2019 by igorpadykov


Power sequence specifications at "IMX6SDLCEC 4.2.1 Power-Up Sequence” says:

“Ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the external components that use both the 1.8 V and 3.3 V supplies).”


I have +3v3 that is the first power to supplying VDD_SNVS_IN and VDD_HIGHT_IN. To prevent this “back voltage” I power all 3,3V peripheric and NVCC_x through a power switch. When this power switch is off (power up sequence is going), I have some mV in peripheric (around 10mv).

I think 10mv is a very low voltage to produce a latch-up or something like that, but I launch the question. Is it safe the power up sequence with 10mv in 3v3v peripherals?