I have some questions regarding the iMX8M Mini EVK design, specifically the LPDDR4 sheet in SOM schematic "8MMINILPD4-CPU" and more general LPDDR4 questions.
- Why is there a 150R resistor termination on the DRAM_CK differential signals?
- This isn't mentioned in the Hardware Design Guide, and hasn't been observed on LPDDR4 designs for other SoCs
- What is the purpose of the DNP 10K resistors R123, R124, R121 & R122 on DRAM_CKE0/1
- The recommendation in the Hardware Design Guide is to use 85 Ohm differential controlled impedance for DDR DQS/CLK. However on other LPDDR4 designs these are routed at 100 Ohms. Why is this recommendation different from the standard used?