i.MX6 SPI, controlled delay of SCLK after CS

[j_brouwer]

Hello,

I'm trying to control a SPI slave (CC1125 transceiver chip) with an i.MX6 (SPI master, MCIMX6X1EVK10AB). The SPI slave has a unique 'flavor' of SPI: When the CS pin is made low, the master needs to wait until MISO is made low as well (which indicates the slave's crystal has become stable) before the first rising edge of SCLK.

We have a possible solution. We can use the CS pin as a GPIO. We have not discovered how to configure the MISO pin as both a GPIO and SPI pin simultaneously, so we will physically split the MISO signal off to a secondary GPIO pin and use that to read its state. An alternative is to configure all SPI pins as GPIO's and write a custom SPI 'driver'. However, we are looking for something a bit more elegant (receiving the same identical signal on two pins of the same chip irks, and we'd like to use the provided drivers instead of reinventing them).

Do you have any advice for us?

Kind regards,

Justin

[igorpadykov · Accepted solution]

Hi Justin

one can try to set for MISO pin SION bit (described in IOMUX Chapter of Reference Manual)

and read corresponding GPIO bit through GPIOx_PSR. Other alternative may be to decrease

spi frequency so SPI slave was always ready.

Best regards
igor
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