iMX 6UL NAND Address cycles definition

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iMX 6UL NAND Address cycles definition

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sugiyamatoshihi
Contributor V

Hi, Yuri,

However, i.MX6UL EVK set column+Row total address byte. 

Reference manual seems wrong.

Best Regards,

Sugiyama

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Yuri
NXP Employee
NXP Employee

Hello,

  Why do You think, that i.MX 6UL uses BOOT_CFG1[1] and BOOT_CFG1[0]

fuses / bits (Nand_Row_address_bytes) as full NAND address? 

Regards,

Yuri.

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toshishisasugiy
Contributor I

Hi, Yuri,

I read EVK user guide IMX6ULEVKHUG.pdf, and it is described as below.

This means BTCFG5 D1=H, D2=H, D3=L, D4=H => CFG1[0]=H, CFG1[5]=H, CFG1[6}=L, CFG1[7]=H

Also, in the schematic SPF-28617_C5.pdf there is below description. This device has 2 column and 3 row address.

It showed CFG1[1]=H because it pulled up by a resistor in the schematic.

This means Nand_Row_address_byte=[11]=5

Best Regards,

Sugiyama

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