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Question asked by Lothar Felten on Oct 1, 2019
Latest reply on Oct 1, 2019 by igorpadykov



I have no clock output on the CSI_MCLK ball. The TRM states that the CSI module is not responsible for the clock output but that it's driven from the CCM directly.


I checked the following registers:


SW_PAD_CTL_PAD_CSI_MCLK (0x20e_0460) -> 0x1b0b0

SW_MUX_CTL_PAD_CSI_MCLK (0x20e_01d4) -> 0x0 (MUX is ALT 0)

CCM_CCGR2 (0x20c_4070) -> 0x0FFF_003C (csi_clk_enable, but I'm not sure if this is for the CSI module)

CCM_CSCDR3 (0x20c_403C) -> 0x14041  (24MHz from osc_clk)


Are there some other registers in the CCM/IOMUX I need to set to output the 24MHz clock?