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i.MX8MM - No Audio Data on SAI3 when capturing

Question asked by Martin Townsend on Sep 24, 2019
Latest reply on Oct 3, 2019 by Martin Townsend

Hi,

 

We have an SGTL5000 connected to SAI3 where the SAI3 is the I2S Master.  We've modified the imx-sgtl5000 machine driver to cater for this and set it so that it doesn't support just playback. We've also modified the driver to remove all the audmux stuff as the i.MX8 MM doesn't have one.  We've ensure all the drivers required are enabled in the kernel.

 

We're connected the codec in the same manner that the WM8524 is connected on the EVK with the exception that we are really interested in Audio capture so we have

I2S_DIN -> SAI3_TXD

I2S_DOUT -> SAI3_RXD

I2S_SCLK -> SAI3_TXC

I2S_LRCLK -> SAI3_TXFS

I2S_MCLK -> SAI3_MCLK

 

The SAI is configured so that the transmitter is asynchronous but the receiver is synchronous, from the reference manual

"If the transmitter bit clock and frame sync are to be used by both the
transmitter and receiver:
• The transmitter must be configured for asynchronous operation and
the receiver for synchronous operation.
• In synchronous mode, the receiver is enabled only when both the
transmitter and receiver are enabled.
• It is recommended that the transmitter is the last enabled and the
first disabled."

 

But when recording we are getting silence.  I have put debug code in imx_pcm_dma_v2_complete and there is nothing in the memory that should be DMA'd to.  The RDR0 register is always zero as well.  If I write data into the memory that should have been DMA'ed it arrives in user space and arecord gets data.  So the problem is somewhere in the SAI.  We have probed all the signals and the clocks are all fine and SAI3_RXD is toggling indicating data is present and not just zeros so we believe codec is working fine.

 

I noticed in the driver the following in fsl_sai_trigger when it starts a capture

 

regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset),
FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);

regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset),
FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset),
FSL_SAI_CSR_SE, FSL_SAI_CSR_SE);

 

According to the reference manual SW shouldn't be writing to bit 30 of the xCSR register but this line does for some reason. There isn't even a bit called SE in the document.  I've tried taking this out but it still doesn't work.

 

Here's a dump of the receive and transmit registers when Trigger start occurs

[ 4085.442364] TRIGGER START
[ 4085.444986] FSL_SAI_TCSR: 0x00000008: 0x90100000
[ 4085.449602] FSL_SAI_TCR1: 0x0000000c: 0x0000007a
[ 4085.454220] FSL_SAI_TCR2: 0x00000010: 0x07000007
[ 4085.458838] FSL_SAI_TCR3: 0x00000014: 0x00000000
[ 4085.463456] FSL_SAI_TCR4: 0x00000018: 0x00010f3b
[ 4085.468074] FSL_SAI_TCR5: 0x0000001c: 0x0f0f0f00
[ 4085.472693] FSL_SAI_RCSR: 0x00000088: 0x90100c01
[ 4085.477311] FSL_SAI_RCR1: 0x0000008c: 0x00000005
[ 4085.481928] FSL_SAI_RCR2: 0x00000090: 0x43000000
[ 4085.486546] FSL_SAI_RCR3: 0x00000094: 0x00010000
[ 4085.491164] FSL_SAI_RCR4: 0x00000098: 0x00010f3b
[ 4085.495780] FSL_SAI_RCR5: 0x0000009c: 0x0f0f0f00

 

I can't see anything obvious from reading the reference manual.  I'm really stuck now as to why we are getting no data being received from the codec when there is data on the RXD line.  Is there something wrong with the SAI configuration above?

 

uname -a returns:

Linux imx8mmevk 4.14.98-imx_4.14.98_2.0.0_ga+g5d6cbeafb80c #1 SMP PREEMPT Tue Sep 24 06:36:55 UTC 2019 aarch64 aarch64 aarch64 GNU/Linux

 

Any help greatly appreciated,

Martin.

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