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Hold time control for NAND flash.

Question asked by Takayuki Ishii on Sep 24, 2019
Latest reply on Oct 7, 2019 by Takayuki Ishii

Hello community,

 

I'm trying to configure GPMI NAND I/F timing for i.MX6Dual.

Current GPIM_TIMING0[DATA_HOLD]=3 and GPIM_TIMING0 register value is a  0x00010303.

But write cycle waveform output only 1cycle width.

Other bit value, GPIM_TIMING0[ADDRESS_SETUP] and GPIM_TIMING0[DATA_SETUP], seems correctly.

 

Do you have some checkpoint to solve this problem?

 

Best regards,

Ishii.

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