I have some question about the chip of P2020.
When I design ddr3 in fly-by mode,Which MCKp/n is best to support the DDR3‘s CLK between MCKp/n[0:5] .
Any MCK pair can be used - they all are functionally identical.
Note that single MCK pair must be used for a memory bank (chip select) - refer to the AN3940, Table 1. DDR3 designer checklist:
"46. Ensure one clock pair is used for each chip-select. The clock pair should follow the address/command/control signal groups in fly-by topology".
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