SDRAM Bandwidth test with the emwin demo

[hongmei_wang3]

Hi,

I am using the RT1050 EV borad to do the SDRAM performance test. I refer to the AN12437SW firmware which shows how to test the sdram read bandwidth, After run the code on the board, the result was as the document described:

##sdram read perf###t1: 361667; t2: 339695; diff: 21972; ns: 36620, datasize: 4096 byte; perf: 111MB/s; g_ms: 0.

As I was focus on whether the SDRAM bandwidth will be enough for the LCD display, so I port the performance test firmware to the SDK demo: emwin_gui_demo. I comment out all the LCD display related function in main function ,just the sdram read bandwidth test functions was ported. But the result was quite wired, which shows:

##sdram read perf###t1: 369488; t2: 328413; diff: 41075; ns: 68458, datasize: 4096 byte; perf: 59MB/s; g_ms: 0.

Q1.Has there anyone who run to this issue? Why this happens?

Q2.How should I test the SDRAM bandwidth with the LCD display.

Attachment (main funciton in emwin_gui_demo):

int main(void)
{
uint32_t time;
volatile uint32_t tmp;
uint32_t g_ms;
uint32_t t1;
uint32_t t2;
uint32_t coreclk = 0;
uint32_t dsize = 4*1024;
uint32_t *ahb_addr = (uint32_t *)0x80000000;

BOARD_ConfigMPU();
BOARD_InitPins();
BOARD_InitSemcPins();
BOARD_BootClockRUN();
BOARD_InitDebugConsole();
coreclk = CLOCK_GetFreq(kCLOCK_CoreSysClk);
CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
/* Set semc clock to 163.86 MHz */
CLOCK_SetMux(kCLOCK_SemcMux, 1);
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
#if( DCACHE_ENABLE ==1 )
PRINTF("DCACHE is enabled!\r\n");
#else
SCB_DisableDCache();
PRINTF("DCACHE is disable!\r\n");
#endif
#if PREFETCH_BUFF_DIS
FLEXSPI->AHBCR &= ~FLEXSPI_AHBCR_PREFETCHEN_MASK;
PRINTF("Prefetch is disable!\r\n");
#else
PRINTF("Prefetch is enable!\r\n");
#endif
if (BOARD_InitSEMC() != kStatus_Success)
{
PRINTF("\r\n SEMC SDRAM Init Failed\r\n");
}

PRINTF("\r\n Start test SDRAM read performance!\r\n");
/* sdram read test */
ahb_addr = (uint32_t *)0x80000000;
g_msCount = 0;
t1 = SysTick->VAL;
#if 1
for (uint32_t i = 0; i < dsize/4; i ++)
{
sdram_readBuffer[i] = ahb_addr[i];
}
__asm("DSB");
#else
memcpy(&sdram_readBuffer[0],(uint32_t *)(ahb_addr),dsize);
__asm("DSB");
#endif
t2 = SysTick->VAL;
g_ms = g_msCount;
time = (((uint64_t)(t1 - t2) * 1000000000) / coreclk);

uint32_t errCount = 0;
for(uint32_t i=0;i<dsize/4;i++)
{
if(sdram_readBuffer[i] != sdram_writeBuffer[i])
{
errCount++;
}
}
if(!errCount)
{
PRINTF("sdram read and write correctly!\r\n");
}
else
{
PRINTF("sdram read and write fail!\r\n");
}
PRINTF("##sdram read perf###t1: %d; t2: %d; diff: %d; ns: %d, datasize: %d byte; perf: %dMB/s; g_ms: %d\r\n",
t1, t2, t1 - t2, time, dsize, (dsize * 1000)/time, g_ms);

// /* invlide the cache range ahb_addr to ahb_addr+dsize */
DCACHE_InvalidateByRange((uint32_t )ahb_addr,dsize);

PRINTF("\r\n SEMC SDRAM Performance test End.\r\n");

//sdram test
while (1)
{
}
}

[hongmei_wang3]

Hi Jeremy,

Yes, You are right. I run the code in sdram_debug project, after I set the read buffer address to SRAM and read data from sdram to sram, the result shows 110MB/s.But I have more question about this:

Q1. My purpose was to test the sdram bandwidth left when LCD display enabled. So If LCD display enabled , the sdram bandwidth should be smaller than it was disabled， right？

Q2. As the ELCDIF controller will take the sdram bandwidth while the SEMC will also take the SDRAM bandwidth. But my test result shows little change for LCD display enable and disable case. Any comments on this?

[jeremyzhou]

Hi hongmei wang,

Thanks for your reply.

Q1. My purpose was to test the sdram bandwidth left when LCD display enabled. So If LCD display enabled , the sdram bandwidth should be smaller than it was disabled， right？

-- The ELCDIF controller wouldn't affect the performance of the SDRAM actually, it only can decrease the time that CUP is occupied by the SDRAM operation.

Have a great day,
TIC

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[jeremyzhou]

Hi hongmei wang,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Q1.Has there anyone who run to this issue? Why did this happen?
-- I guess it's caused by the code is not run in the ITCM.
Q2.How should I test the SDRAM bandwidth with the LCD display?
--  AN12437SW code is suited for kinds of code run case and different application, so you can use this testing code for your application.
However, I hope you should have the concept that the SDRAM performance is related to code run area, nothing with the application function.

Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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