Hello,
I am using RT1060 with MCUXpresso IDE 11.0.1 and checked AN12437 i.MX RT Series Performance Optimization application note to learn about how to put instructions in ITCM using AT_QUICKACCESS_SECTION_CODE, but this is function by function.
Is there any way to put all of functions in a single source code/object file into ITCM?
Thanks,
Tom
Thank you, Kerry. I am not sure if my question is clear enough, but I would like to put the entire source file or object file into ITCM SRAM. For instance, let's say I have math.c and math.o, I would like to put all of functions from math.o in ITCM SRAM.
Will wait for the update. Thank you for working on this.
Hi Tomohiro,
Do you check the MCUXpresso_IDE_User_Guide.pdf, chapter: 18.15.1 Relocating code from FLASH to RAM?
You can find the user guider already tell you how to process it.
This information is also from our IDE department, you can find it can relocated the whole .c file to the RAM.
Have a great day,
Kerry
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Hi Kerry, yes I saw your previous response, the guide document provides good information, so I tried that, but it gave me another question as I posted on this thread (still waiting for approval by moderator). Please check that question.
Hi Tomohiro Inoue ,
Please check the MCUXpresso IDE install path:
C:\nxp\MCUXpressoIDE_11.0.0_2516
MCUXpresso_IDE_User_Guide.pdf, chapter: 18.15.1 Relocating code from FLASH to RAM
You will find the detail information.
Wish it helps you!
Have a great day,
Kerry
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Hi Kerry,
Thank you for your reply. I have followed "18.15.1 Relocating code from FLASH to RAM" and created these 3 files in linkscripts folder.
Looks this modifications worked, but the issue I have now is this. This modification is put all of specified code into SRAM_DTC, but I don't have enough space left for the code even though I have enough space left on both SRAM_ITC and SRAM_OC.
On MCU settings, it is like this and if I modify this, the program does not work at all:
SRAM_DTC 0x20000000 0x20000
SRAM_ITC 0x0 0x20000
SRAM_OC 0x20200000 0xc0000
How can I put the specific code on SRAM_ITC? or how can I increase SRAM_DTC?
I am using MIMXRT1060-EVK.
Thanks,
Tom
Hi Tom,
Thanks for your updated information.
About the DTC and ITC , please check this application note, you will know how to configure it:
https://www.nxp.com/docs/en/application-note/AN12077.pdf
If you still have questions about it, please kindly let me know.
Wish it helps you!
Have a great day,
Kerry
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Hi Kerry,
Thank you for your reply. I have checked AN12077.pdf and now I know there are 2 ways to configure FlexRAM.
2.1.1.1.Static configuration
2.1.1.2. Runtime configuration
I have 5 questions as below.
1. Regarding Static configuration, can you let me know how I can do this on MCUXpresso IDE?
2. Static configuration says FUSE FlexRAM bank configuration. Is this really using Fuse so that this can be done only one time and you cannot change the configuration?
3. Regarding Runtime configuration, P.21 has sample assembly code. Can you let me know which file I can put this code on MCUXPresso IDE?
4. I guess if I modify RAM assignment, I also need to modify Linker configuration on MCUXpresso. Am I correct?
5. I learned from MCUXpresso_IDE_User_Guide.pdf that I can put those object on SRAM_DTC. Can you let me know how I can put those objects on SRAM_ITC using .ldt files? If I modify main_data.ldt, then everything goes to SRAM_DTC, but I would like to use SRAM_ITC since this is instruction code.
I am using MCUXpresso IDE v11.0.1_2563.
Thanks,
Tom
Hi inoue-san
1. Regarding Static configuration, can you let me know how I can do this on MCUXpresso IDE?
There is no such function for now.
いまのところ起動時にFlexRAMを設定するような機能はなさそうです。
2. Static configuration says FUSE FlexRAM bank configuration. Is this really using Fuse so that this can be done only one time and you cannot change the configuration?
I do not know because I have never used Fuse, but you can change the TCM configuration with IOMUXC_GPR_GPR17 if I don't use Fuse.
Fuseを使ったことがないので実際のところはわかりませんが、上記のようにResetハンドラでIOMUXC_GPR_GPR17変更してITCM=256KB, DTCM=256KBとして使用することができます。
3. Regarding Runtime configuration, P.21 has sample assembly code. Can you let me know which file I can put this code on MCUXPresso IDE?
Please see fsl_flexram.c/h. and sample code is "boards\evkmimxrt1060\driver_examples\flexram\ram_allocate".
There is no assembler example, but I think the usage of FLEXRAM_AllocateRam in the sample code will be helpful.
アセンブラの例はないですが、サンプルコードのFLEXRAM_AllocateRamの使い方が参考になると思います。
4. I guess if I modify RAM assignment, I also need to modify Linker configuration on MCUXpresso. Am I correct?
Yes. An example of setting ITCM and DTCM to 256 KB each is as follows:
5. I learned from MCUXpresso_IDE_User_Guide.pdf that I can put those object on SRAM_DTC. Can you let me know how I can put those objects on SRAM_ITC using .ldt files? If I modify main_data.ldt, then everything goes to SRAM_DTC, but I would like to use SRAM_ITC since this is instruction code.
sorry, I don't know how to put an object to ramfunc section in MCUXpresso_IDE. I use "__attributr__ section".
Best Regards,
T.Kashiwagi
Hi Kashiwagi-san,
Thank you for your reply.
4. I guess if I modify RAM assignment, I also need to modify Linker configuration on MCUXpresso. Am I correct?
Yes. An example of setting ITCM and DTCM to 256 KB each is as follows:
The capture shows that the size of SRAM_ITC is 0x40000, but the size of SRAM_DTC is 0x3fc00. Is this typo? Or do I need to use 0x3fc00 to have 256KB of SRAM_DTC?
My current RAM allocation is like this. This is still for 128KB DTC/ITC. Do I need to split OCRAM like your capture?
DTC 0x20000000 0x20000
ITC 0x0 0x20000
OC 0x20200000 0xc0000
Actually, I have already made the changes like this, but it didn't work.
DTC 0x20000000 0x40000
ITC 0x0 0x40000
OC 0x20200000 0x80000
It doesn't stop at the main as usual when I start debugging and I don't see any output from UART.
The table 3 of this application note is for RT1050 / RT106x, but total RAM of RT1050 and 1062 are different.
The application note also says that the minimum OCRAM is 64KB because of ROM code. 1060 Reference Manual says 2 OCRAM regions:
2028_0000 202F_FFFF 512KB OCRAM - FlexRAM
2020_0000 2027_FFFF 512KB OCRAM2
I am getting confused. Is all of 1024KB RAM FlexRAM on 1060?
Thanks,
Tom
Hi Inoue-san
The capture shows that the size of SRAM_ITC is 0x40000, but the size of SRAM_DTC is 0x3fc00. Is this typo? Or do I need to use 0x3fc00 to have 256KB of SRAM_DTC?
It is not typo. I use the area from 0x2000000-0x2000400 as a vector table. DTCM_SIZE depends on your software design.
My current RAM allocation is like this. This is still for 128KB DTC/ITC. Do I need to split OCRAM like your capture?
DTC 0x20000000 0x20000
ITC 0x0 0x20000
OC 0x20200000 0xc0000
If you want to use ITCM and DTCM as a 256KB area, you need to set it. Otherwise, the linker will not recognize the ITCM and DTCM areas as 256KB
Actually, I have already made the changes like this, but it didn't work.
DTC 0x20000000 0x40000
ITC 0x0 0x40000
OC 0x20200000 0x80000
It doesn't stop at the main as usual when I start debugging and I don't see any output from UART.
Has a Hard Fault occurred? Also make sure that the program has been copied to TCM.
The table 3 of this application note is for RT1050 / RT106x, but total RAM of RT1050 and 1062 are different.
It is the setting when using fuse. ROM code requires at least 64 KB of RAM for its execution. So You can use it freely after Boot ROM is finished.
The application note also says that the minimum OCRAM is 64KB because of ROM code. 1060 Reference Manual says 2 OCRAM regions:
2028_0000 202F_FFFF 512KB OCRAM - FlexRAM
2020_0000 2027_FFFF 512KB OCRAM2
I am getting confused. Is all of 1024KB RAM FlexRAM on 1060?
No, OCRAM2 is not FlexRAM. OCRAM2 can not be set to TCM.
Best Regards,
T.Kashiwagi
Hi Kashiwagi-san,
The table 3 of this application note is for RT1050 / RT106x, but total RAM of RT1050 and 1062 are different.
It is the setting when using fuse. ROM code requires at least 64 KB of RAM for its execution. So You can use it freely after Boot ROM is finished.
Do you mean when the CPU core is executing function ResetISR, it already finished boot code execution so that you can assign whatever you want?
Actually, I have already made the changes like this, but it didn't work.
DTC 0x20000000 0x40000
ITC 0x0 0x40000
OC 0x20200000 0x80000
It doesn't stop at the main as usual when I start debugging and I don't see any output from UART.
Has a Hard Fault occurred? Also make sure that the program has been copied to TCM.
No, I don't see Hard Fault. When I click 'Debug', then MCUXpresso download the code into the flash. In normal case, it stops at main function, but in this case, it doesn't stop.
After power cycle the board, if I click 'Debug', then I see "0 available SWD Devices detected" error message.
Do you see any issue on this RAM assignment on MCUXpresso?
DTC 0x20000000 0x40000
ITC 0x0 0x40000
OC 0x20200000 0x80000
The application note also says that the minimum OCRAM is 64KB because of ROM code. 1060 Reference Manual says 2 OCRAM regions:
2028_0000 202F_FFFF 512KB OCRAM - FlexRAM
2020_0000 2027_FFFF 512KB OCRAM2I am getting confused. Is all of 1024KB RAM FlexRAM on 1060?
No, OCRAM2 is not FlexRAM. OCRAM2 can not be set to TCM.
So, RT1060 has fixed 512KB for OCRAM2, and if you want to increase more, then you can map FlexRAM at 2028_0000. Am I correct?
Thanks,
Tom
Hi Inoue-san
Do you mean when the CPU core is executing function ResetISR, it already finished boot code execution so that you can assign whatever you want?
Yes. Please see "8.5.1 Internal ROM/RAM memory map" in RM.
No, I don't see Hard Fault. When I click 'Debug', then MCUXpresso download the code into the flash. In normal case, it stops at main function, but in this case, it doesn't stop.
After power cycle the board, if I click 'Debug', then I see "0 available SWD Devices detected" error message.
Probably the main function has not been reached. Press the break button after pressing the Debug button. Check the CPU register and TCM contents at that time.
Do you see any issue on this RAM assignment on MCUXpresso?
DTC 0x20000000 0x40000
ITC 0x0 0x40000
OC 0x20200000 0x80000
No. I think there is no problem. But the default size of ITCM/DTCM is 128KB. The TCM size must be changed to 256KB before the code / data is copied.
So, RT1060 has fixed 512KB for OCRAM2, and if you want to increase more, then you can map FlexRAM at 2028_0000. Am I correct?
Yes. For example, the following RAM layout is possible.
ITC 0x0 0x20000
DTC 0x20000000 0x20000
OC 0x20200000 0xC0000
(ITCM=128KB, DTCM=128KB, OCRAM+OCRAM2=768KB)
Best Regards,
T.Kashiwagi
Hi Kashiwagi-san,
I am pasting my RestISR in below. Can you please check if the TCM size is changed to 256KB before the code/data is copied and they are copied appropriately?
Thanks,
Tom
#include "fsl_flexram.h"
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors.reset")))
void ResetISR(void) {
// Disable interrupts
__asm volatile ("cpsid i");
/** TCM and OCRAM Config */
IOMUXC_GPR->GPR17 = 0xAAAAFFFFu;
IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK;
IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(9); /** 256KB */
IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK;
IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(9); /** 256KB */
IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK;
IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(kFLEXRAM_BankAllocateThroughBankCfg);
#if defined (__USE_CMSIS)
// If __USE_CMSIS defined, then call CMSIS SystemInit code
SystemInit();
#else
// Disable Watchdog
volatile unsigned int *WDOG1_WCR = (unsigned int *) 0x400B8000;
*WDOG1_WCR = *WDOG1_WCR & ~(1 << 2);
volatile unsigned int *WDOG2_WCR = (unsigned int *) 0x400D0000;
*WDOG2_WCR = *WDOG2_WCR & ~(1 << 2);
// Write watchdog update key to unlock
*((volatile unsigned int *)0x400BC004) = 0xD928C520;
// Set timeout value
*((volatile unsigned int *)0x400BC008) = 0xFFFF;
// Now disable watchdog via control register
volatile unsigned int *RTWDOG_CS = (unsigned int *) 0x400BC000;
*RTWDOG_CS = (*RTWDOG_CS & ~(1 << 7)) | (1 << 5);
#endif // (__USE_CMSIS)
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if !defined (__USE_CMSIS)
// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
// will setup the VTOR register
// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
*pSCB_VTOR = (unsigned int)g_pfnVectors;
}
#endif // (__USE_CMSIS)
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
// Reenable interrupts
__asm volatile ("cpsie i");
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main();
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
Hi Inoue-san.
I think the TCM setting is fine.
However, I don't know about copying ramfunc code and data. The code starting with the comment “Copy the data sections from flash to SRAM” will copy the code and data to the RAM.
Please Check the MAP file to see what data is actually copied. "__data_section_table" consists of LOADADDR, ADDR, and SIZE as follows (SIZE bytes are copied from the LOADADDR address to the ADDR address.).
And Make sure that it is copied by the debugger.
*This is my project MAP file(IMXRT1060-EVK/IMXRT1060-EVK_APL at develop · tkashi-github/IMXRT1060-EVK · GitHub )
*(SORT_BY_ALIGNMENT(.isr_vector))
.isr_vector 0x80000000 0x2b8 ./startup/startup_mimxrt1062.o
0x80000000 g_pfnVectors
0x80000000 __Vectors
0x800002b8 . = ALIGN (0x4)
0x800002b8 __section_table_start = .
0x800002b8 __data_section_table = .
0x800002b8 0x4 LONG 0x80092b00 LOADADDR (.data)
0x800002bc 0x4 LONG 0x80092b00 ADDR (.data)
0x800002c0 0x4 LONG 0x1260 SIZEOF (.data)
0x800002c4 0x4 LONG 0x8007c358 LOADADDR (.data_RAM2)
0x800002c8 0x4 LONG 0x80400000 ADDR (.data_RAM2)
0x800002cc 0x4 LONG 0x0 SIZEOF (.data_RAM2)
0x800002d0 0x4 LONG 0x8007c358 LOADADDR (.data_RAM3)
0x800002d4 0x4 LONG 0x81000000 ADDR (.data_RAM3)
0x800002d8 0x4 LONG 0x0 SIZEOF (.data_RAM3)
0x800002dc 0x4 LONG 0x8007c358 LOADADDR (.data_RAM4)
0x800002e0 0x4 LONG 0x0 ADDR (.data_RAM4)
0x800002e4 0x4 LONG 0x6530 SIZEOF (.data_RAM4)
0x800002e8 0x4 LONG 0x80082888 LOADADDR (.data_RAM5)
0x800002ec 0x4 LONG 0x20000400 ADDR (.data_RAM5)
0x800002f0 0x4 LONG 0x10274 SIZEOF (.data_RAM5)
0x800002f4 0x4 LONG 0x80092afc LOADADDR (.data_RAM6)
0x800002f8 0x4 LONG 0x20200000 ADDR (.data_RAM6)
0x800002fc 0x4 LONG 0x0 SIZEOF (.data_RAM6)
0x80000300 0x4 LONG 0x80092afc LOADADDR (.data_RAM7)
0x80000304 0x4 LONG 0x20240000 ADDR (.data_RAM7)
0x80000308 0x4 LONG 0x0 SIZEOF (.data_RAM7)
0x8000030c 0x4 LONG 0x80092afc LOADADDR (.data_RAM8)
0x80000310 0x4 LONG 0x20260000 ADDR (.data_RAM8)
0x80000314 0x4 LONG 0x0 SIZEOF (.data_RAM8)
0x80000318 __data_section_table_end = .
0x80000318 __bss_section_table = .
0x80000318 0x4 LONG 0x80094200 ADDR (.bss)
0x8000031c 0x4 LONG 0x93b34 SIZEOF (.bss)
0x80000320 0x4 LONG 0x80400000 ADDR (.bss_RAM2)
0x80000324 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
0x80000328 0x4 LONG 0x81000000 ADDR (.bss_RAM3)
0x8000032c 0x4 LONG 0x800000 SIZEOF (.bss_RAM3)
0x80000330 0x4 LONG 0x6530 ADDR (.bss_RAM4)
0x80000334 0x4 LONG 0x0 SIZEOF (.bss_RAM4)
0x80000338 0x4 LONG 0x20010680 ADDR (.bss_RAM5)
0x8000033c 0x4 LONG 0x1fa44 SIZEOF (.bss_RAM5)
0x80000340 0x4 LONG 0x20200000 ADDR (.bss_RAM6)
0x80000344 0x4 LONG 0x3fc00 SIZEOF (.bss_RAM6)
0x80000348 0x4 LONG 0x20240000 ADDR (.bss_RAM7)
0x8000034c 0x4 LONG 0x0 SIZEOF (.bss_RAM7)
0x80000350 0x4 LONG 0x20260000 ADDR (.bss_RAM8)
0x80000354 0x4 LONG 0x0 SIZEOF (.bss_RAM8)
0x80000358 __bss_section_table_end = .
0x80000358 __section_table_end = .
By the way, In which section is RestISR located?
Best Regards,
T.Kashiwagi
Hi Kashiwagi-san,
Here is my section table. I am not sure if this is ok. I tried check with debugger, but the values on memory at 0x6008b384 is like this:
00000000 40404040 00000000 40404040
0x20000000 is like this:
23010020 54000045 00001032 20000000
const char *report_type_str[] is at 0x20000000 and its value is ASCII string, so looks the value is wrong.
ResetISR is at 0x60002308. It is also 40404040 00000000 40404040 00000000, so maybe the debugger cannot read the memory value correctly.
Do you see any issue on my section table?
0x60002000 __vectors_start__ = ABSOLUTE (.)
*(SORT_BY_ALIGNMENT(.isr_vector))
.isr_vector 0x60002000 0x2b8 ./startup/startup_mimxrt1062.o
0x60002000 g_pfnVectors
0x60002000 __Vectors
0x600022b8 . = ALIGN (0x4)
0x600022b8 __section_table_start = .
0x600022b8 __data_section_table = .
0x600022b8 0x4 LONG 0x6008b384 LOADADDR (.data)
0x600022bc 0x4 LONG 0x20000000 ADDR (.data)
0x600022c0 0x4 LONG 0xdc SIZEOF (.data)
0x600022c4 0x4 LONG 0x6008b384 LOADADDR (.data_RAM2)
0x600022c8 0x4 LONG 0x0 ADDR (.data_RAM2)
0x600022cc 0x4 LONG 0x0 SIZEOF (.data_RAM2)
0x600022d0 0x4 LONG 0x6008b384 LOADADDR (.data_RAM3)
0x600022d4 0x4 LONG 0x20200000 ADDR (.data_RAM3)
0x600022d8 0x4 LONG 0x0 SIZEOF (.data_RAM3)
0x600022dc 0x4 LONG 0x6008b384 LOADADDR (.data_RAM4)
0x600022e0 0x4 LONG 0x80000000 ADDR (.data_RAM4)
0x600022e4 0x4 LONG 0x0 SIZEOF (.data_RAM4)
0x600022e8 __data_section_table_end = .
0x600022e8 __bss_section_table = .
0x600022e8 0x4 LONG 0x200000dc ADDR (.bss)
0x600022ec 0x4 LONG 0x1abc8 SIZEOF (.bss)
0x600022f0 0x4 LONG 0x0 ADDR (.bss_RAM2)
0x600022f4 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
0x600022f8 0x4 LONG 0x20200000 ADDR (.bss_RAM3)
0x600022fc 0x4 LONG 0x0 SIZEOF (.bss_RAM3)
0x60002300 0x4 LONG 0x80000000 ADDR (.bss_RAM4)
0x60002304 0x4 LONG 0x0 SIZEOF (.bss_RAM4)
0x60002308 __bss_section_table_end = .
0x60002308 __section_table_end = .
Thanks,
Tom
Hi Tomohiro Inoue,
Thanks for the reply from T.Kashiwagi.
Now, add some comment about your 5 question.
2. Static configuration says FUSE FlexRAM bank configuration. Is this really using Fuse so that this can be done only one time and you cannot change the configuration?
Answer: Just as T.Kashiwagi has replied you, you can use IOMUXC_GPR_GPR17 register to modify the configuration in run time.
But after boot, the configuration will use the fuse data, but please note, fuse area just can be modified one times. So, normally, in your design phase, you can modify the register to realize it, but in the product phase, you can modify the fuse.
5. I learned from MCUXpresso_IDE_User_Guide.pdf that I can put those object on SRAM_DTC. Can you let me know how I can put those objects on SRAM_ITC using .ldt files? If I modify main_data.ldt, then everything goes to SRAM_DTC, but I would like to use SRAM_ITC since this is instruction code.
Answer:
If you want to use the SRAM_ITC, you can move the SRAM_ITC to the first one in memory configuration editor.
You can try it on your side.
If you still have questions about it, please kindly let me know.
Have a great day,
Kerry
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Hi Kerry,
5. I learned from MCUXpresso_IDE_User_Guide.pdf that I can put those object on SRAM_DTC. Can you let me know how I can put those objects on SRAM_ITC using .ldt files? If I modify main_data.ldt, then everything goes to SRAM_DTC, but I would like to use SRAM_ITC since this is instruction code.
Answer:
If you want to use the SRAM_ITC, you can move the SRAM_ITC to the first one in memory configuration editor.
If I do this, then everything goes to ITC, but as far as I read the application note, instruction code should go to ITCM and data should go to DTCM. So, I would like to keep data on DTCM.
https://www.nxp.com/docs/en/application-note/AN12077.pdf
Thanks,
Tom
Hi Tom,
If you want to put the data in the DTCM, and other code still in the ITCM, I think you can define some section, then put your data in that DTCM section:
In factor, I am the RT engineer, not the MCUXpresso IDE engineer, if you have more details about the MCUXpresso IDE usage, I think you also create the question the MCUXpresso IDE region:
Wish it helps you!
Have a great day,
Kerry
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Hi Inoue-san.
Do you see any issue on my section table?
No. I think there is no problem with the section table.
It seems that the data is not written correctly in FlashROM.
Please compare the binary file with the read memory. And First, check whether the DCD table and the vector table are written correctly. If a DCD table is included, the ROM starts with "FCFB".
If no binary file has been generated, enable the next line in the post-build step.
arm-none-eabi-objcopy -v -O binary "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.bin"
Best Regards,
T.Kashiwagi
Hi Kashiwagi-san,
After loading "hello world" example, I could use Debug Mode only one time.
Below is what I can see on the debugger. This matches with the .bin file.
0x60000000 46 43 46 42 00 04 01 56 00 00 00 00 01 03 03 00 FCFB...V........
0x60000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x60000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x60000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x60000040 00 00 00 00 00 04 06 00 00 00 00 00 00 00 00 00 ................
0x60000050 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x60000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x60000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x60000080 EB 04 18 0A 06 32 04 26 00 00 00 00 00 00 00 00 ë....2.&........
0x60000090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Thanks,
Tom
I could put breakpoint on ResetISR. When I start the debugging, Eclipse shows green highlight on this line:
__asm volatile ("cpsid i");
I could do step over with "hello world" example, but I could't with my project. After clicking "step over" button once, Eclipse shows this.
Any suggestion to try something?
Thanks,
Tom
Hi Inoue-san,
According to ABFSR, Asynchronous fault on DTCM interface has been occurred.
3.3.9. Auxiliary Bus Fault Status Register ARM Information Center
Please check which instruction caused Hard Fault when you executed "step in".
Is the instruction trying to write to an invalid address?
Best Regards,
T.Kashiwagi
Hi Kashiwagi-san,
I am not quite sure if there is any difference between Step Over and Step Into here since the very first instruction is this:
__asm volatile ("cpsid i");
I did Step Into (F5) on that and got the same Hard Fault with additional window as below.
Thanks,
Tom Inoue
Hi Inoue-san.
I am not quite sure if there is any difference between Step Over and Step Into here since the very first instruction is this:
__asm volatile ("cpsid i");
Does it mean that a hard fault occurs just by executing "__asm volatile ("cpsid i") ;" in your project?
I think that there is no possibility of a hard failure because you can run the "hello world" example ".
So I think that the program is not written correctly.
As a confirmation again, are the PC and SP at the time of break in ResetISR set to the intended values?
Best Regards.
T.kashiwagi
Hi Kerry Zhou san
The same phenomenon as the following thread appears.
Can you tell me if you know any solution?
Best Regards,
T.Kashiwagi
I just get the project, and will test it which is shared in that post, and give reply later.
Please give me more time, thanks.
After I test it, I will also let you know.
Best Regards,
Kerry
Thank you Kerry-san.
Hi Inoue-san.
Please modify the connect script as Kerry-san says in the following thread.
Best Regards,
T.Kashiwagi
Thank you, Kerry.
Hi Kashiwagi-san,
On that thread, the processor is RT1052 instead of 1062 and the memory size is different from what I want. So I modified the script as below and it worked with debugger.
But the issue is, it doesn't work without debugger.
360 REM ====== Configure FlexRAM ====== https://community.nxp.com/thread/517877
370 print "Configure FlexRAM for 0KB OC RAM (+dedicated 512KB), 256KB I-TCM, 256KB D-TCM"
380 REM TCM CTRL Poke 0x400B0000 - to force RAM clocking and set wait states = b100
390 Poke32 this 0x400B0000 0x4
400 REM IOMUXC_GPR17 0x400AC044 - this sets bitfield allocation of FlexRAM 32KB banks to OC 256KB b01, I 128KB b11, D 128KB b10
410 Poke32 this 0x400AC044 0xAAAAFFFF
420 REM IOMUXC_GPR16 0x400AC040 - this sets enables for I and DTCM and the source of the TCM config = 0x200007
430 Poke32 this 0x400AC040 0x200007
440 print "Finished"
450 REM ===============================
I guess this is the code to do the same with the script above, so I put this in RestISR, but didn't help.
FLEXRAM->TCM_CTRL = 4;
IOMUXC_GPR->GPR17 = 0xAAAAFFFFu;
IOMUXC_GPR->GPR16 = 0x200007;
This is the previous code I used.
IOMUXC_GPR->GPR17 = 0xAAAAFFFFu;
IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK;
IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(9); /** DTCM 256KB */
IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK;
IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(9); /** ITCM 256KB */
IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK;
IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(kFLEXRAM_BankAllocateThroughBankCfg);
I appreciate your help for supporting me, but now it is working with debugger and it doesn't without debugger, so it is difficult to debug more, I think. If you have any suggestions, please let me know. Otherwise, I think I just need to use the default RAM assignment.
Thanks,
Tom Inoue
Hi Tom,
If you want to modify the FlexRAM, I think you can modify the fuse related bit, then even you without debugger, you also don't need to modify the related register in the code, do you mind to modify the FlexRAM fuse to your designed configuration?
Anyway, I will test it on my side with and without the debugger.
Any updated information, I will let you know.
Best Regards,
Kerry
Hi Kerry,
As you mentioned before, fuse area just can be modified one time, so I don't want to modify that at this moment. Thank you for working on this.
Thanks,
Tom Inoue
I totally understand you don't want to burn the fuse now.
I still need more time to find the way about the issue after downloading.
Please keep patient!
Best Regards,
Kerry
I have reproduced your problems, I will do more research, please wait patiently, thank you!
Have a great day,
Kerry
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Hi Tomohiro Inoue,
I already help you to check it with our MCUXpresso IDE department about putting the single code in ITCM.
Any updated information, I will let you know.
Please keep patience, thanks!
Have a great day,
Kerry
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