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ENET_SetSMI at 180 MHz for LPC546XX

Question asked by Thorsten Wilmer on Sep 21, 2019
Latest reply on Sep 25, 2019 by Felipe García

Hi

 

I'm trying to debug my ethernet phy communication - which does not work yet.

 

My Core Clock is configured to 180 Mhz, which leads to  a divisor of 42 in the following code:

 

void ENET_SetSMI(ENET_Type *base)
{
uint32_t crDiv;
uint32_t srcClock_Hz = CLOCK_GetCoreSysClkFreq() / 1000000U;

if ((srcClock_Hz >= 20U) && (srcClock_Hz < 35))
{
crDiv = 2;
}
else if ((srcClock_Hz >= 35) && (srcClock_Hz < 60))
{
crDiv = 3;
}
else if ((srcClock_Hz >= 100) && (srcClock_Hz < 150))
{
crDiv = 1;
}
else
{
crDiv = 0;
}

base->MAC_MDIO_ADDR = ENET_MAC_MDIO_ADDR_CR(crDiv);
}

 

Is this intentional?

 

The Datasheet allows

0x0 CSR clock = 60-100 MHz; MDC clock = CSR clock/42
0x1 CSR clock = 100-150 MHz; MDC clock = CSR clock/62
0x2 CSR clock = 20-35 MHz; MDC clock = CSR clock/16
0x3 CSR clock = 35-60 MHz; MDC clock = CSR clock/26

 

So I would expect the test to be inclusive of 150 MHz

else if ((srcClock_Hz >= 100) && (srcClock_Hz <= 150))

 

Or may be even 180 MHz?

 

To my surprise this loop is also not left:

 

base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK;
while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK)
{
}

 

 

I have enabled the following clocks:

 

CLOCK_EnableClock(kCLOCK_Eth);
CLOCK_EnableClock(kCLOCK_Dma);

 

And I have called 

ENET_SetSMI(ENET);

 

This command returns 0xFFFF for all PHY Addresses,

      PHY_Read(ENET, i, PHY_ID1_REG, &idReg);

 

so the bus most likely does not work yet, my PHY may be broken or in a not initalized state... Or I have not yet succesfully enable the Ethernet module. I'm using LPC54616 on a custom board with THA1102, so the example code does not work directly.

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