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Read SRAM occur error

Question asked by jiran jiang on Sep 20, 2019
Latest reply on Sep 30, 2019 by David Tosenovjan


 I have divided a piece of SRAM in the App program(MCU: S32R274), which will be initialized once only when the power on. other reset conditions are not initialized. the purpose of this is mainly for som information interaction between bootloader and App. However, after i do this, the first function reset of the app will be ok, but when i do the second function reset, a BUS_DRERR(Read bus error on data load or linefill) will be generated, the RGM_DES.F_EDR = 1,RGM_FES.F_ST_DONE = 1 , RGM_FES.F_SOFT_FUNC = 1,  why is this?

reset command :

   MC_ME.MCTL.R = 0x00005AF0 ;
   MC_ME.MCTL.R = 0x0000A50F;
   while(1); // wait reset


the initialization code is as follow(Startup.s) :

;# check power on flag
   e_li r7,-360448   
   se_lwz r7,0(r7)
   se_andi r7,1
   se_extzb r7
   se_cmpi r7,0
   e_mcrf cr7
   mfcr r7
   e_rlwinm r7,r7,28,0,3
   mtcrf 128,r7
   e_beq sram_Init ;# check the RGM.DES.B.F_POR , if == 1 , init the divided SRAM, ==0 do not init.


;# __SRAM_COMMON_SIZE = 128 bytes.  __SRAM_COMMON_BASE_ADDR = 0x40000000

   e_lis r5, __SRAM_COMMON_SIZE@h # Initialize r5 to size of SRAM (Bytes)
   e_or2i r5, __SRAM_COMMON_SIZE@l
   e_srwi r5, r5, 0x7 # Divide SRAM size by 128
   mtctr r5 # Move to counter for use with "bdnz"
   ;# Base Address of the internal SRAM
   e_lis r5, __SRAM_COMMON_BASE_ADDR@h
   e_or2i r5, __SRAM_COMMON_BASE_ADDR@l
   ; # Fill SRAM with writes of 32GPRs
   e_li r0, 0
   e_li r1, 0
   e_li r2, 0
   e_li r3, 0
   e_li r4, 200
   e_stmw r0,0(r5) # Write all 32 registers to SRAM
   e_addi r5,r5,128 # Increment the RAM pointer to next 128bytes
   e_bdnz blapcomsram_loop # Loop for all of SRAM
   e_li r7,-360448
   se_lwz r6,0(r7)
   se_bseti r6,31
   se_stw r6,0(r7)


;# other sram init



thank you!