1 In fine correction method,
ENET 1588 timer should run under 50MHz CLK, thus 50MHz*43ns = 0x7fff fff made the nanosecond register reach to 0x7fff fff every second , but this CLK may drift to other frequency so we have to adjust addend register to adjust the frequency ,under which 43ns was add to system timer, if the frequency drift to 66MHz so we make addend register to 2^32/1.32 , thus 43ns was added to nanosecond every 1.32 66MHz clk , make result as under 50MHz CLK, is my understanding right?
2 On page 864 of manual, described ref clk drifted to 65MHz,66MHz,67MHz, what if the ref CLK drift to 45MHz, then 45/50=0.9, addend value should = 2^32/0.9? but this overflows,
here is my test data time offset between slave and master:slaveSyncTime - masterSyncTime
if offset<0 means , slave needs to run faster, we have to make addend register value bigger, what if addend register value is already 0xffff ffff?
3 I use the addend value adjustment algorithm on page 865,but slave clk offset to master clk hop, the offset may be -200ms, 125us,11ms. -28ms 140us.. ... offser not stable, slave clk not locked to master
bellow is my way, please correct me
FreqCompensationValue_0 = 0xffff ffff
MasterClockTime_n_1: timestamp got in last followUp msg
MasterClockTime_n: timestamp got in current followUp msg
SlaveClockTimen_n_1 :timestamp got when last sync msg arrived
SlaveClockTimen_n :timestamp got when current sync msg arrive
MasterClockCount_n = MasterClockTime_n - MasterClockTime_n_1 (MasterClockCount_n int32 with unit of nanosecond)
SlaveClockCount_n = SlaveClockTimen_n - SlaveClockTime_n_1 (SlaveClockCount_n int32 with unit of nanosecond)
FreqScaleFactor_n= (MasterClockCount_n + MasterClockCount_n - SlaveClockCount_n )*1.0/SlaveClockCount_n
FreqCompensationValue_n = FreqScaleFactor_n * FreqCompensationValue_n_1
I set FreqCompensationValue_0 = 0xffff ffff, but I found that if FreqScaleFactor_n >1(slave needs to run faster?) and FreqCompensationValue_n_1 = 0xffff ffff, take FreqScaleFactor_n = 1.045412 for example,
FreqCompensationValue_1 = 1.045412* FreqCompensationValue_0 = 1.045412*0xffff ffff = 0xffff ffff,
that means addend register is not adjusted.
where is the wrong understanding?