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what are the actual memory ranges for the dynamic chips selects?

Question asked by Eileen Radzwion on Sep 20, 2019
Latest reply on Sep 26, 2019 by jeremyzhou

In the LPC546xx user manual, in table 634, address ranges for the different chip select pins are listed.  But, the address ranges for at least the dynamic cs's are first not big enough for the range listed.  second, they do not match what is shared in LPC54608.h:

 

/** EMC CS base address */
#define EMC_CS0_BASE (0x80000000u)
#define EMC_CS1_BASE (0x90000000u)
#define EMC_CS2_BASE (0x98000000u)
#define EMC_CS3_BASE (0x9C000000u)
#define EMC_DYCS0_BASE (0xA0000000u)
#define EMC_DYCS1_BASE (0xB0000000u)
#define EMC_DYCS2_BASE (0xC0000000u)
#define EMC_DYCS3_BASE (0xD0000000u)
#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}
#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}

 

 

and the UM:

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