Looking at "Chip Errata for the i.MX 6Solo/6DualLite Rev. 7, 04/2019" (IMX6SDLCE.pdf), I have found the following errata which may affect our application:
They reference the following ARM errata numbers:
However, I have been unable to find these in any of the ARM errata documentation for Cortex A9 or PL310. Could you please point me at the source for these errata?
Looking at the errata conditions, and suggested workarounds, it seems to me the only safe way to circumvent these data corruption issues is to use write-through cache. This has a heavy impact on performance, but data corruption must be avoided for us. Am I right in saying this?
I've attached the errata document for your convenience.