AnsweredAssumed Answered

Clock Sharing Feasibility for "MCIMX6Q6AVT10AD"

Question asked by Arif Kanganolli on Sep 12, 2019
Latest reply on Sep 15, 2019 by Wigros Sun

Hello,

 

Greetings,

 

I am using MCIMX6Q6AVT10AD on my design, i have four DDR3L( MT41K256M16TW-107 AIT:P TR) chips interfacing with i.MX6.

 

I am using CLK0 i.e DRAM_SDCLK_0 for all the four chips and i have left CLK1 Not connected.

 

Kindly provide your valuable feedback on this, whether this is the the right way or no??

 

Thank You

 

Regards,

Arif

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