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Why NOR mode can't work with GPCM for IFC at the same time ?

Question asked by Fei Xia duan on Sep 11, 2019
Latest reply on Sep 17, 2019 by Bulat Karymov

As our custom T1042 board, IFC controller connect a 32MB nor flash(16-bit width) by CS0 and connect a 8-bit CPLD by CS2. CS0 was configured with NOR mode through MSEL bit of OR. and CS2 was configured with GPCM mode through MSEL bit of OR. There's no problem if access each at different time, but if accessing the CPLD, we do erase/write to nor flash, it will make the read/write CPLD not reliable, all registers read from CPLD turn-ed to be all zeros. That's very strange. once this problem happened, the cs signal of CS2 for CPLD seems to be abort-ed by IFC controller. we dump-ed the 0xFFE125800 register, it's value turn-ed to be 0x00400000, that means the transaction to CPLD was abort-ed during erasing/writing to NOR flash. 

 

But If I turn the CS2 MSEL into NOR mode. the word turn to be peace. But I can't explain the problem, there may be some potential design bug for IFC controller side.

 

Log when problem happened

fffd40400 : 03 00 c3 09 03 00 c3 09 03 00 c3 09 03 00 c3 09 : ................
fffd40410 : 07 00 c7 09 07 00 c7 09 07 00 c7 09 07 00 c7 09 : ................
fffd40420 : 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b : ................
fffd40430 : 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b : ................
fffd40440 : 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b : ................
fffd40450 : 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b : ................
fffd40460 : 08 00 c0 0b : ....
0x00000000
fffd40400 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : ................
fffd40410 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : ................
fffd40420 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : ................
fffd40430 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : ................
fffd40440 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : ................
fffd40450 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : ................
fffd40460 : 00 00 00 00 : ....
0x00400000

 

.......

 

After 5 seconds after the NOR flash erase and write complete, accessing CPLD turn to be good again.

fffd40400 : 03 00 02 00 03 00 02 00 03 00 02 00 03 00 02 00 : ................
fffd40410 : 07 00 02 09 07 00 02 09 07 00 02 09 07 00 02 09 : ................
fffd40420 : 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b : ................
fffd40430 : 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b : ................
fffd40440 : 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b : ................
fffd40450 : 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b 08 00 c0 0b : ................
fffd40460 : 08 00 c0 0b : ....
0x00400000

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