We have a custom PCB using a T1040 processor with an NvSRAM attached to the IFC bus, running in GPCM mode. We notice that once a power-down sequence is initiated by our power manager, in response to the boards input supplies going off, there is a sequence of transactions on many of the IFC signals. This includes WE and CS signals which unintentionally enables writes to the NvSRAM with whatever is on the IFC bus at the time. When we turn the card back on, certain locations in the NvSRAM are corrupted. This seems to occur whether the T1040 is in reset or not during power-down.
We don't suspect crosstalk as a number of IFC signals exhibit the same pattern, including an unused CLE signal which has a very short trace to a pull-up. The fact that CLE transitions in the same way points the finger towards the T1040 rather than the NvSRAM as only the T1040 connects to this net.
I have attached a scope trance which shows the NvSRAM chip select CS2 (yellow) and CLE (blue) with the transactions occurring just before the +1V8 supply to the IFC bus turns off (Where the signals start to roll off).
We have managed to 'solve' the issue by changing our power-down sequence so that the +1V8 supply to the IFC turns off first before the T1040 core and +3V3 supply but it seems like a strange behaviour.
Has anyone seen anything similar? Any thoughts on what might be causing these transactions?