The Dumb PMIC mode is assumed, and I am planning to connect the PMIC_ON_REQ terminal on the i.MX 7Dual side and the terminal that powers on / off in the level state on the PMIC side.
After applying a voltage to the VDD_SNVS_IN pin, will it start in Smart PMIC mode during Power on sequence (because it was described as “0” at RESET)?
The level signal is expected as the PMIC_ON_REQ signal.
However, does it have to be able to start with a pulse to start up in Smart PMIC mode?
Or, if you have a way or procedure to start with a level instead of a pulse, please let me know.