AnsweredAssumed Answered

RMII with imx6sx doesn't work on kernel v4.9

Question asked by Tomasz Parka on Sep 3, 2019
Latest reply on Sep 6, 2019 by igorpadykov

Hello,
We have custom modules based on imx6sx.
Our firmware based on Yocto Project Version 2.5 (sumo) - everythig works fine of it.
Last time we updated Yocto to versio 2.7 (warrior), but Ethernet doesn't work on it.
So kernel was updated from 4.1 to 4.9 (we tested also 4.19).
We use RMII mode (50Mhz + SION bit is set).
So when SION bit is set (according to description in imx6sx-pinfunc.h) the kernel (v4.9) hang on Network configuration.

 

What could possibly be wrong?

 

Here you have part of our dts file:
#include "imx6sx.dtsi"
...
&fec1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_enet1>;
    phy-reset-gpios = <&gpio2 0 0>;
    phy-mode = "rmii";
    status = "okay";
};
...
pinctrl_enet1: enet1grp {
            fsl,pins = <
                MX6SX_PAD_ENET1_MDIO__ENET1_MDIO    0x1b0b1
                MX6SX_PAD_ENET1_MDC__ENET1_MDC        0x1b0b1
                MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN     0x1b0b1
                MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x0051
                MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0    0x1b0b1
                MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1    0x1b0b1
                MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0x1b0b1
                MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0    0x1b0b1
                MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1    0x1b0b1
                MX6SX_PAD_ENET1_COL__GPIO2_IO_0        0x10b0
            >;
        };
        
        
Here you have part of our patches:
Index: kernel-source/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
===================================================================
--- kernel-source.orig/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ kernel-source/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -424,9 +424,9 @@
 #define IMX6SX_GPR1_VADC_SW_RST_MASK            (0x1 << 19)
 #define IMX6SX_GPR1_VADC_SW_RST_RESET            (0x1 << 19)
 #define IMX6SX_GPR1_VADC_SW_RST_RELEASE        (0x0 << 19)
-#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK        (0x3 << 13)
-#define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK        (0x3 << 17)
-#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT        (0x3 << 13)
+#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK        (0x1 << 13)
+#define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK        (0x1 << 17)
+#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT        (0x1 << 13)
 
 #define IMX6SX_GPR4_FEC_ENET1_STOP_REQ            (0x1 << 3)
 #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ            (0x1 << 4)
Index: kernel-source/arch/arm/mach-imx/mach-imx6sx.c
===================================================================
--- kernel-source.orig/arch/arm/mach-imx/mach-imx6sx.c
+++ kernel-source/arch/arm/mach-imx/mach-imx6sx.c
@@ -84,7 +84,7 @@ static void __init imx6sx_enet_clk_sel(v
         regmap_update_bits(gpr, IOMUXC_GPR1,
                    IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
         regmap_update_bits(gpr, IOMUXC_GPR1,
-                   IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
+                   IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK);
     } else {
         pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
     }
Index: kernel-source/arch/arm/boot/dts/imx6sx-pinfunc.h
===================================================================
--- kernel-source.orig/arch/arm/boot/dts/imx6sx-pinfunc.h
+++ kernel-source/arch/arm/boot/dts/imx6sx-pinfunc.h
@@ -330,7 +330,7 @@
  * also connected to that pin and using respective function as input (e.g.
  * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B).
  */
-#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                    0x0090 0x03D8 0x0760 0x1 0x1
+#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                    0x0090 0x03D8 0x0760 0x11 0x1
 #define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD                   0x0090 0x03D8 0x0644 0x2 0x1
 #define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B                       0x0090 0x03D8 0x0000 0x3 0x0
 #define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK                      0x0090 0x03D8 0x0000 0x4 0x0
 Index: kernel-source/arch/arm/mach-imx/clk-imx6sx.c
===================================================================
--- kernel-source.orig/drivers/clk/imx/imx/clk-imx6sx.c
+++ kernel-source/drivers/clk/imx/clk-imx6sx.c
@@ -617,8 +617,8 @@ static void __init imx6sx_clocks_init(st
     imx_clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
     imx_clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
     imx_clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
-    imx_clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
-    imx_clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
+        imx_clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 50000000);
+    imx_clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 50000000);
 
     /* Audio clocks */
     imx_clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);

Outcomes