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Whether GPIO_3 CKO2 can give SYS_MCLK for SGTL5000

Question asked by Hariharan Veerappan on Aug 30, 2019
Latest reply on Aug 30, 2019 by igorpadykov



Interface details,

GPIO_3 CKO2 is connected with SYS_MCLK of SGTL5000. We tried to generate MCLK from IMX6, but we could not able get any clock on CLKO2 pin.


&ssi2 {     
        assigned-clocks = <&clks IMX6QDL_CLK_PLL4>,
                          <&clks IMX6QDL_PLL4_BYPASS>,
                          <&clks IMX6QDL_CLK_SSI2_SEL>,
                          <&clks IMX6QDL_CLK_CKO2_SEL>,
                          <&clks IMX6QDL_CLK_CKO2>;
        assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>,
                                 <&clks IMX6QDL_CLK_PLL4>,
                                 <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>,
                                 <&clks IMX6QDL_CLK_CKO2_SEL>;
        assigned-clock-rates = <737280000>, <0>, <0>;
        status = "okay";


Configured PIN MUX,

MX6QDL_PAD_GPIO_3__CCM_CLKO2            0x130b0


        codec: sgtl5000@2a {
                compatible = "fsl,sgtl5000";
                reg = <0x2a>;
                clocks = <&clks IMX6QDL_CLK_CKO2>


Please share your inputs how to configure the CLK Output on GPIO_3 for SYS_MCLK of SGTL5000.