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iMXRT FlexIO SPI CS high time between two transfers

Question asked by Johann Zimmermann on Aug 29, 2019
Latest reply on Sep 11, 2019 by Johann Zimmermann

Hi everyone,


I would like to control an ADC chip via FlexIO SPI.
How can I influence the clock cycle between the slave select
negating and before the next transfer?


In SDK examples this time is always an SPI clock.
I need longer time for CS high before the next transfer started.
Is that possible?