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LPC43xx SDRAM EMC D/DQM signal ordering

Question asked by leecoakley on Aug 27, 2019
Latest reply on Sep 12, 2019 by Felipe García

I'm working on an LPC4357 based design which uses the EMC with 32-bit SDRAM.  BGA256 package.


According to the EMC documentation the controller always accesses the SDRAM in bursts of four words. This means that the ordering of the data signals and byte enables does not matter, and the D0-D31 and DQM0-3 signals can be routed in any order within their respective groups without affecting the operation of the external memory.  Is this correct?


I would love to know because it would make my task of routing the SDRAM drastically simpler.  I'm pretty sure this will work but I would like some confirmation by more experienced people here.


To spell it out, this means connecting the SDRAM to the EMC like this:

D0 - D13

D1 - D27

D2 - D5