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About Power mode transitions

Question asked by on Aug 26, 2019
Latest reply on Aug 27, 2019 by igorpadykov



There are two questions about Table 6-8 Power mode transitions in i.MX 7 Dual Applications Processor Reference Manual.


(1) Does this mean that timer interrupt is enabled by LP Time Alarm Enable in SNVS_LP Control Register (LPCR)?
Which field should I check to see if an interrupt was asserted?


(2) If DP_EN of SNVS_LP Control Register (LPCR), can PMIC_ON_REQ signal be set to 0 in TOP?

Table 6-8. Is the Configuration with internal PMIC column of Power mode transitions Dumb PMIC?


Best reguards