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DDR_PHY programming issue on IMX8M board

Question asked by Vyacheslav Bondarev on Aug 26, 2019
Latest reply on Sep 9, 2019 by Yuri Muhin

Hello!

 

Trying to bring up DDR controller on out own board based on IMX8M processor. Without success for now,

We are using DDR4 memory. Tried to use MSCALE_ddr_tool utility, log and DDR script is attached.

 

There is a problem with our board with DDR data bus connection -- DQ pins swapped. As I was able to understand from Reference manual, this may be fixed by setting appropriate values to DDR_PHY.DWC_DDRPHYA_DBYTEn.Dq[0-7]LnSel[0:3], but wasn't able to write to that registers from u-boot or from DDR script of MSCALE_DDR_tool utility. Writing from U-Boot SPL has no effect, reading back as zeroes(actually, all DDR_PHY registers reads as zeroes). It seems some basic initalization wasn't done for DDR_PHY(clocks or something like that)...

 

We are using uboot-imx version imx_v2017.03_4.9.88_2.0.0_ga, u-boot config imx8mq_arm2(by the way, from what board this config is and can we look at it's schematic?).

 

How we can set DDR_PHY.DWC_DDRPHYA_DBYTEn.Dq[0-7]LnSel[0:3] registers from U-Boot?

 

Additionally, I can't figure out DDR_PHY register address calculation principle. In RM we have DDR_PHY base 0x3c000000, DWC_DDRPHYA_DBYTE0 block offset 0x10000, and Dq0LnSel register offset 0x140, so address should be 0x3c010140. But in MX8M_LPDDR4_RPA_v23.xlsx file(which was used as a reference to generate "memory set" commands for DS) address specified for that register is 0x3C040280. I can understand that register offset should be multiplied by 2, because it's 16-bit word offset, but why block offset multiplied by 4?? How to determine register addresses of DDR_PHY block? For our experiments with U-Boot we used addresses from MX8M_LPDDR4_RPA_v23.xlsx.

 

Regards,

Vyacheslav Bondarev

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