AnsweredAssumed Answered

How do I configure pins in FreeRTOS, uboot and Linux for an i.MX?

Question asked by Paul Quiring on Aug 20, 2019
Latest reply on Aug 23, 2019 by Radhika Somaiya

Hello Community,

 

I want to configure the Pad GPIO1_IO02 to use alternate mode 5. Furthermore, I don't want to use the default settings of the pad as shown in table "Table 4-1. Pin Assignments" of the document IMX6SXRM.pdf.

 

default settings
HYS - DISABLED
PUS -
PUS_100KOHM_PD
PUE - KEEP
PKE - ENABLED
ODE - DISABLED
SPEED - 100MHZ
DSE - 43_OHM
SRE - SLOV

 

settings I want to use

HYS - ENABLED
PUS - 47K Ohm Pull Up
PUS_100KOHM_PD
PUE - KEEP
PKE - ENABLED
ODE - DISABLED
SPEED - 150MHz @ 3.3V
DSE - 43_OHM
SRE - SLOV

 

  • What would the patch for the Yoko build look like (uboot, Linux) in order to get the desired settings for the pad GPIO1_IO02?
  • What must be changed in the case I2C2_BASE of the function "void configure_i2c_pins(I2C_Type* base)" in order to achive the settings I want to use. Below is the piece of code that needs to be changed. It belongs to the FreeRTOS BSP v1.0.1 for the ai development board (FreeRTOS_BSP_1.0.1_iMX6SX\examples\imx6sx_ai_m4\pin_mux.h).
case I2C2_BASE:
// I2C2 iomux configuration
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_SION_MASK;
IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT = IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY(1);
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_SION_MASK;
IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT = IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY(1);

IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_MASK;

IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_MASK;
break;

 

 

 

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