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i.MX 6SX SABRE Board DDR3 Layout SI/Timing analysis

Question asked by Thomas Stegmeijer on Aug 20, 2019
Latest reply on Aug 29, 2019 by gusarambula

We are designing a board with a IMX6 SoloX, this board is partially based upon the I.MX 6SX sabre board. We are also using 2 4Gb DDR3L chips. My PCB stack-up is a bit different compared to the sabre board but 50 ohm SE en differential pair widths etc are quite similar. I could copy the DDR3 layout from the sabre board and make slight adjustments to match the widths and lengths of the vias etc. 

 

But the sabre board has the Adress and command group partially routed on outer layers and the other signals via an inner layer. As far as I can measure the signals that travel via the inner layer are length matched to the traces that run via the outer layers. But has been accounted for the propogation delay difference between inner and outer layers and the extra vias? 

Or has SI and timing analysis been done on the Sabre design and proved it would not be needed?

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