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DDR Stress Tester

Question asked by 康茂 李 on Aug 20, 2019
Latest reply on Sep 5, 2019 by Rita Wang

您好!

我使用DDR Stress Tester Tool V3.0.0对开发板的DDR进行矫正测试,主芯片为IMX6DL,在进行DDR Calibration时,提示矫正失败,错误信息如下:

ARM Clock set to 1GHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
============================================

Current Temperature: 46
============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
MPWLHWERR register read out for factory diagnostics:
MPWLHWERR PHY0 = 0x78787878
MPWLHWERR PHY1 = 0x00000000


HW WL cal status: no suitable delay value found for byte 4

HW WL cal status: no suitable delay value found for byte 5

HW WL cal status: no suitable delay value found for byte 6

HW WL cal status: no suitable delay value found for byte 7
Write leveling calibration completed but failed, the following results were found:
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x004C004D
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00430043
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001F001F
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001F001F
Write DQS delay result:
Write DQS0 delay: 77/256 CK
Write DQS1 delay: 76/256 CK
Write DQS2 delay: 67/256 CK
Write DQS3 delay: 67/256 CK
Write DQS4 delay: 31/256 CK
Write DQS5 delay: 31/256 CK
Write DQS6 delay: 31/256 CK
Write DQS7 delay: 31/256 CK


WARNING: write-leveling calibration value is greater than 1/8 CK.
Per the reference manual, WALAT must be set to 1 in the register MDMISC(0x021B0018).
This has been performed automatically.
However, in addition to updating the calibration values in your DDR initialization,
it is also REQUIRED change the value of MDMISC in their DDR initialization as follows:

MMDC_MDMISC (0x021b0018) = 0x00011740


Error: failed during write leveling calibration

 

请教一下,这可能是什么原因导致的?谢谢

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