Hi Mark, The failure we're seeing mimics thread DDR calibration issue on a custom iMX6Solo board .
However all the required voltages are present in our case. We're using both 24 MHz and 32.768 kHz external crystals. The clocks look clean at around 1.1 Vpp. We're using two 4 Gbit DDR3 chips from Alliance operating on 1.35V. Along with the NXP iMX6 Solo processor we are using the NXP PMIC MMPF0200F6AEP. The DRAM_RESET pin is high (1.35 V). SDCKE0 and SDCKE1 are both low. DDR_VREF is 0.68 V (comes from PMIC).
Here's the test tool window:
Below is the text output of the tool after downloading the .inc script and then running the calibration:
DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:12:28
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.4
SRC_SBMR1(0x020d8004) = 0x0100d072
SRC_SBMR2(0x020d801c) = 0x01000001
ARM Clock set to 800MHz
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 32, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 1024MB
Current Temperature: 49
DDR Freq: 297 MHz
Start write leveling calibration...
running Write level HW calibration
MPWLHWERR register read out for factory diagnostics:
MPWLHWERR PHY0 = 0x00001e1e
HW WL cal status: no suitable delay value found for byte 2
HW WL cal status: no suitable delay value found for byte 3
Write leveling calibration completed but failed, the following results were found:
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x000D0013
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F001F
Write DQS delay result:
Write DQS0 delay: 19/256 CK
Write DQS1 delay: 13/256 CK
Write DQS2 delay: 31/256 CK
Write DQS3 delay: 31/256 CK
Error: failed during write leveling calibration
Since we can't get by the "simple" leveling routine, there must be something obvious that we are missing.