I'm designing a board based on the LPC4357 which uses external SDRAM. I have read a lot about this, including the app notes and posts here, but it never hurts to run the specifics past people.
All the SDRAM lines have been length matched to 30mm +/- 7mm. The clock line is made longer, 44mm, based on Bernhard Fink 's advice that this will provide more timing margin. The question is: is this length matching good enough and is the clock line sufficiently longer than the other signals for reliable operation? I can easily adjust the clock line to be longer or shorter by a long way. The others I can match to perhaps +/- 4mm with some effort.
The SDRAM is an ISSI is42s32800. 102 MHz operating frequency.
The LPC4357 is the FET256 BGA package. The clock pin used is CLK0. The other CLK pins are not used for anything else.
This is a six layer board with dedicated ground and power planes. The SDRAM signals are routed on all four signal planes. The signals are routed through a maximum of two vias on their way to the SDRAM, not counting the dogbone escapes from the BGA.
Address pins A0/A6/A7/A8 have a 10K pulldown to set the boot mode. A9 has a 10K pullup for ISP. The 10K value is an a** pull, please let me know if I should use a different value.
Any suggestions greatly welcomed, as you may save me quite a lot of money.