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i.MX6ULL SPI question

Question asked by m.c on Aug 14, 2019
Latest reply on Aug 15, 2019 by Yuri Muhin

In i.Mx6ULL reference manual.

 

1. For single burst. Is it mean transfer single FIFO and waiting for software to write data to FIFO? SS is an don't care pin, until FIFO transfer complete?

 

 

2. For multi burst. Is it mean transfer different FIFO, SS pin will assert if any FIFO transfer complete? Then transfer another FIFO? The burst won't finish until all FIFO transfer complete?

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