About the following three questions
About IRQ56 to IRQ63 in Table 7-1 of i.MX 7Dual Applications Processor Reference ManualI want to know the register names for enabling / disabling INT7 to INT0?
GPIO1 Combined interrupt indication for GPIO1 signal 0 throughout 15
Does an interrupt occur if any valid interrupt condition from signal0 to signal15 is met?
Does the combined interrupt indication also occur under the interrupt condition from INT7 to INT0?