Following are specification of our board
CPU : MPC8270 (Big Endian)
Clock: Bus:100Mhz, Core: 400 Mhz
SDRAM: 64MB(Chip size) (13 rows, 11 columns, 4 banks, port: 8 bit) (Total Chips = 8) making 512MB total size
If we enable Data parity Pins (DP[0-7]), we get continuous parity errors which is reflected in TESCR registers. But the operating system is running fine (Showing no RAM corruption i.e. No parity error).
We have interfaced data bus(inverted i.e. Big Endian style) as shown in attached file "Data_interface.PNG". While the Data parity pins (DP[0-7]) interfacing is not interfaced in Big endian Mode (Not inverted) i.e. DP0 is connected to D0 etc.
(1) Is our interfacing for Parity is wrong? Should it be connected invertly i.e. DP0 connected to D7 etc.
(2) The parity error is generated but the core read/write transactions are good on SDRAM. Which means that
there is no parity error in SDRAMs. There must be some hardware interfacing issue. Is this approach right?
(3) What are the workarounds for this problem?