I have a weird problem where the Timer1 match register interrupt handler is failing to be serviced when a GPDMA terminal count interrupt fires a few microseconds beforehand and the DMA IRQ handler is actively running. The Timer1 IRQ handler is being serviced normally when no other interrupts are pending or actively being serviced, the trouble only happens when the DMA handler is active. My reading of the Cortex-M3 NVIC is that:
- If the interrupts are the same priority, the Timer1 interrupt should be set to pending and handled after the DMA handler is completed
- If the Timer1 interrupt is a higher priority, the Timer1 interrupt handler will pre-empt the DMA interrupt handler and execute, returning to the DMA handler when completed
I have confirmed the following:
- Both interrupts are enabled in ISER0
- Both interrupts are serviced normally when they are not pending at the same time
- In case there was a priority problem, I lowered the priority of GPDMA to the lowest value (31) using IPR6 before enabling DMA using ISER0. Timer1 is the highest priority (0).
Has anyone encountered a problem like this? Am I missing something obvious?