AnsweredAssumed Answered

iMX8 MIPI CSI - base address switching Change Err

Question asked by Joe Sandom on Aug 5, 2019

I'm currently in the process of integrating an image sensor (RAW12/10/8) with the potential of outputting 4K at 60fps and full HD at 120fps with the iMX8MQ SOM by SolidRun. The carrier board in use is the Hummingboard Pulse and the image sensor has a custom adaptor board to meet the pin-out requirements of the iMX8MQ SOM.

 

The image sensor in use has been verified with the Nvidia Jetson TX2 developer kit and the drivers have been ported over to the iMX8. The device drivers and device tree nodes have been added and i2c communication with the image sensor has been verified. Based on the iMX8 System Reference Manual, the mx6s_capture.c driver has been modified to allow for RAW10 configuration and the following format has been added as a supported format; 

 

        .name       = "RAWRGB10 (SBGGR10)",
        .fourcc     = V4L2_PIX_FMT_SBGGR10,
        .pixelformat    = V4L2_PIX_FMT_SBGGR10,
        .mbus_code  = MEDIA_BUS_FMT_SBGGR10_1X10,
        .bpp        = 2,

 

The following commands were entered in order to test streaming; 

 

v4l2-ctl --set-fmt-video=width=1920,height=1080,pixelformat=BG10

v4l2-ctl --stream-mmap

The base device tree entry for the mipi_csi_1 node is listed as the following;

 

 

    mipi_csi_1: mipi_csi1@30a70000 {
        compatible = "fsl,mxc-mipi-csi2_yav";
        reg = <0x0 0x30a70000 0x0 0x1000>; /* MIPI CSI1 Controller base addr */
        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MQ_CLK_DUMMY>,
                <&clk IMX8MQ_CLK_CSI1_CORE>,
                <&clk IMX8MQ_CLK_CSI1_ESC>,
                <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
        clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
        assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
                 <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
                 <&clk IMX8MQ_CLK_CSI1_ESC>;
        assigned-clock-rates = <266000000>, <150000000>, <66000000>;
        power-domains = <&mipi_csi1_pd>;
        csis-phy-reset = <&src 0x4c 7>;
        phy-gpr = <&gpr 0x88>;
        status = "disabled";
    };

 

Upon starting the stream, the following error is seen: 'Base address switching change err'. From my understanding of the reference manual, the embedded DMA controller will write the frame buffer 1 and then buffer 2, the start address should be aligned in word and set in the CSIDMASA-FB1 and CSIDMASA-FB2 registers. From looking at the debug output, buffer 1 is written and then the base address switching change error occurs. Does anyone know why this is happening? From looking at previous questions in the forums, it seems like a platform clock issue. Can anyone confirm this?

 

Debug output;

 

[   54.388015] [mx6s_capture]: start_streaming
[   54.403813] [mx6s_capture]: csi enabled in mipi mode
[   54.408850] [mxc-mipi-csi2_yav]: Enable stream
[   54.413447] [mxc-mipi-csi2_yav]: power management runtime resume
[   54.447708] [mxc-mipi-csi2_yav]: csi2 phy reset
[   54.452450] [mxc-mipi-csi2_yav]: hc config - num lanes: 2
[   54.457992] [mcx-mipi-csi2_yav]: csi2 phy gpr - i2c write success
[   54.464368] [mxc-mipi-csi2_yav]: csi2 phy gpr (enable csi)
[   54.470026] MIPI CSI2 HC register dump, mipi csi0
[   54.474903] MIPI CSI2 HC num of lanes     0x100 = 0x1
[   54.480120] MIPI CSI2 HC dis lanes        0x104 = 0xc
[   54.485343] MIPI CSI2 HC BIT ERR          0x108 = 0x0
[   54.490506] MIPI CSI2 HC IRQ STATUS       0x10C = 0x8
[   54.495669] MIPI CSI2 HC IRQ MASK         0x110 = 0x1ff
[   54.501060] MIPI CSI2 HC ULPS STATUS      0x114 = 0x0
[   54.506283] MIPI CSI2 HC DPHY ErrSotHS    0x118 = 0x0
[   54.511449] MIPI CSI2 HC DPHY ErrSotSync  0x11c = 0x0
[   54.516673] MIPI CSI2 HC DPHY ErrEsc      0x120 = 0x0
[   54.521836] MIPI CSI2 HC DPHY ErrSyncEsc  0x124 = 0x0
[   54.527061] MIPI CSI2 HC DPHY ErrControl  0x128 = 0x0
[   54.532278] MIPI CSI2 HC DISABLE_PAYLOAD  0x12C = 0x0
[   54.537500] MIPI CSI2 HC DISABLE_PAYLOAD  0x130 = 0x0
[   54.542663] MIPI CSI2 HC IGNORE_VC        0x180 = 0x1
[   54.547886] MIPI CSI2 HC VID_VC           0x184 = 0x1
[   54.553103] MIPI CSI2 HC FIFO_SEND_LEVEL  0x188 = 0x40
[   54.558413] MIPI CSI2 HC VID_VSYNC        0x18C = 0x0
[   54.563578] MIPI CSI2 HC VID_SYNC_FP      0x190 = 0x0
[   54.568802] MIPI CSI2 HC VID_HSYNC        0x194 = 0x0
[   54.573967] MIPI CSI2 HC VID_HSYNC_BP     0x198 = 0x0
[   54.979258] [mx6s_capture]: dequeue buf
[   55.013062] Nextfb: 0, SkipFrame: 0
[   55.016610] [mx6s_capture]: csi frame done called
[   55.021434] [mx6s_capture]: Update CSI DMA FB1 buffer
[   55.021451] [mx6_capture]: dequeue buf finished
[   55.026635] base address switching Change Err.
[   55.031085] [mx6s_capture]: vidioc qbuf
[   55.039657] mx6s_videobuf_prepare (vb=0xffff80009b558800) 0xffff80003c300000 0
[   55.046991] [mx6s_capture]: buf_prepare, size image = 4147200
[   55.052909] mx6s_videobuf_queue (vb=0xffff80009b558800) 0xffff80003c300000 4147200
[   55.060589] [mx6s_capture]: buf_queue
[   55.063055] Nextfb: 1, SkipFrame: 1
[   55.067782] [mx6s_capture]: dequeue buf
[   55.067785] skip frame 0
<[   55.079721] base address switching Change Err.
[   55.113064] Nextfb: 1, SkipFrame: 0
[   55.116612] skip frame 0
[   55.129722] base address switching Change Err.
[   55.163065] Nextfb: 1, SkipFrame: 0
[   55.166613] skip frame 0
[   55.179723] base address switching Change Err.
[   55.213059] Nextfb: 1, SkipFrame: 0
[   55.216598] skip frame 0
[   55.229723] base address switching Change Err.
[   55.263066] Nextfb: 1, SkipFrame: 0
[   55.266613] skip frame 0

 

Any help would be greatly appreciated!

Outcomes