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FRDM-KL25Z source clock for UART0 in polling mode

Question asked by Mato Cica on Aug 3, 2019
Latest reply on Aug 5, 2019 by Mato Cica

Hi NXP Community,

Please, what source clock should I use for UART0 in polling mode on FRDM-KL25Z?
I suppose that should be MCGFLLCLK clock or MCGPLLCLK/2. If so, which on of them?

Thanks in advance,

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