I was looking for some more in depth information about how to use the dual cores of the LPC55S6x.
Is there an elaborate document I could read to clear out some of the pitfalls?
Let me point out some grey zones for me.
- it is optimal to let the CPU0 and CPU1 run from different code-sources (flash and SRAMX). But if you don't, what will happen.
Will one CPU wait for the other to finish the instruction fetch?
Will there be a collision with some error trap?
Will false instructions be fed to slave CPU? ....
Now let's say CPU0 is running from Flash and CPU1 from SRAMX.
- Sharing RAM: I would like CPU0 and CPU1 to access a shared area of RAM with data in it needed for both CPUs.
How do I properly share an SRAM block/range?
How do I make sure that the only 1 CPU is accessing it at the same time (I've read the part about mutex, but this only seems to work for 1 variable)?
- How about peripherals: CPU0 uses a set of peripherals spread over different buses and CPU1 as well.
How do I avoid that accessing these peripherals don't cause any bus errors/collisions?
Are there any mutexes for this?
Does every bus have it's own hw-mutex or does some software mutex need to be implemented?
So some help pointing me in the correct direction would be much appreciated.