- I am looking at enabling the code cache controller on the K65 to improve performance.
- I utilize DMA for peripheral to memory and memory to peripheral transfer.
- I know cache and DMA don't normally work good together and the normal operation is to invalidate the cache before/after, read/write respectively.
- From the Table 30-1 it shows that SRAM is non-cacheable. Given this if I make sure that all access with DMA occurs within SRAM would I need to invalidate the cache still?