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SEMC SRAM Performance

Question asked by Michael Rooker on Jul 29, 2019
Latest reply on Sep 13, 2019 by Yuri Muhin

In a previous post I mentioned that I am using a 1052 core in a design in conjunction with an Altera Cyclone 5 FPGA.
The ARM core using the SEMC accesses a piece of memory within the FPGA made to look like SRAM.
I now have it transferring into the ARMS internal ram instead of SDRAM avoiding 2 transfers through the SEMC.
The performance on the SEMC seems sluggish and I would like to optimize it if possible (future designs will incorporate HyperRam to increase performance) but I do not have time to re-spin the hardware at this point.


The SRAM configuration is setup to appear as ADMUX, 16 bit wide and we are using a 166Mhz clock.
I have a while(1) loop that takes a pointer and reads the memory location over and over so I get minimal overhead from CPU instructions.
The read access for a single 16 bit word seems to be around 80ns (CE active low), this is acceptable but the problem is the idle state time. No matter what I do this time will not drop below 70 to 80ns. I can make it longer by introducing
processing between accesses but under normal conditions I am doing nothing else in this loop but a read. I do not see a configuration parameter to shorten this time but it seems that a hit like that every read is excessive.
I have tried a write in the same loop and the idle time is much shorter so I do not know what I am missing at this point. Any help would be appreciated.