I am trying to debug the firmware on two boards using the I-Jet JTAG debugging probe and IAR IDE. My problem is that when using one of these boards IAR fails to initialize the software debugging in the correct Program Counter (PC) position, while when using the other board IAR successfully starts the software debugging in the correct PC location (function "main" of the firmware).
The target boards contain the NXP i.MX512 CPU and both have identical hardware, except for the DDR2 manufacturer. The debug with I-Jet and IAR occurs successfully on the board using Micron MT47H64M16NF-25E IT:M DRAM and it fails on the board using ISSI IS43DR16640C-25DBLI DRAM.
I have already tested the JTAG connection to the i.MX512 CPU on both boards and both are working correctly with my Corelis JTAG probe using IEEE 1149.1 JTAG compliant mode, so the CPU-to-JTAG hardware seems OK. I have also ran NXP's "DDR Stress Tester for MX51" on both boards and both pass on test frequencies greater than the target frequency (200MHz), so the CPU-to-DDR hardware also seems OK.
I think I may be missing some configuration on the side of I-Jet/IAR to make the debugging work with the ISSI DRAM board. I attached the logs of the successful debug and the failed debug for comparison, but I don't know what to make of it so far.
Could anyone help me with this?